CPC G11C 16/26 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a plurality of memory cells configured to store data; and
a processing device coupled to the plurality of memory cells, the processing device configured to manage optimization target data that at least initially includes read levels in addition to a target trim, wherein
the target trim corresponds to an adjustment level used to adjust voltage for reading a portion of the plurality of memory cells; and
the optimization target data is managed based on
iteratively calibrating the read levels based on associated results of reading the stored data; and
removing one or more calibrated read levels from the optimization target data when the one or more calibrated read levels satisfy a target condition.
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