US 11,721,399 B2
Memory system with dynamic calibration using a trim management mechanism
Michael Sheperek, Longmont, CO (US); Larry J. Koudele, Erie, CO (US); and Steve Kientz, Westminster, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 18, 2021, as Appl. No. 17/504,467.
Application 17/504,467 is a continuation of application No. 16/775,099, filed on Jan. 28, 2020, granted, now 11,177,006.
Application 16/775,099 is a continuation of application No. 15/981,810, filed on May 16, 2018, granted, now 10,566,063, issued on Feb. 18, 2020.
Prior Publication US 2022/0036957 A1, Feb. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/26 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of memory cells configured to store data; and
a processing device coupled to the plurality of memory cells, the processing device configured to manage optimization target data that at least initially includes read levels in addition to a target trim, wherein
the target trim corresponds to an adjustment level used to adjust voltage for reading a portion of the plurality of memory cells; and
the optimization target data is managed based on
iteratively calibrating the read levels based on associated results of reading the stored data; and
removing one or more calibrated read levels from the optimization target data when the one or more calibrated read levels satisfy a target condition.