US 11,721,397 B2
Power saving and fast read sequence for non-volatile memory
Jianzhi Wu, Santa Clara, CA (US); Jia Li, San Francisco, CA (US); and Yanjie Wang, San Jose, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Dec. 28, 2020, as Appl. No. 17/135,071.
Prior Publication US 2022/0208276 A1, Jun. 30, 2022
Int. Cl. G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 11/5671 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a page of memory cells, each of the memory cells connected to one of a plurality of word lines and arranged in one or more strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states; and
a control circuit coupled to the plurality of word lines and the one or more strings and configured to perform a read operation to read the memory cells by applying a first sequence of read voltages and a reverse read operation to read the memory cells by applying a second sequence of read voltages different from the first sequence, wherein, to perform the reverse read operation, the control circuit is configured to:
supply a first bit line voltage to one or more strings and, while supplying the first bit line voltage, identify the memory cells having threshold voltages that are less than a first data state threshold voltage,
subsequent to identifying the memory cells having threshold voltages that are less than a first data state threshold voltage, supply the first bit line voltage to one or more strings and, while supplying the first bit line voltage, identify the memory cells having threshold voltages that are less than a second data state threshold voltage, the second data state threshold voltage being less than the first data state threshold voltage, and
subsequent to identifying the memory cells having threshold voltages that are less than the second data state threshold voltage, supply a voltage to inhibit conduction currents of the one or more strings of the memory cells identified as having threshold voltages that are less than the second data state threshold voltage and, while supplying the voltage to inhibit the conduction currents, identify the memory cells having threshold voltages that are less than a third data state threshold voltage, the third data state threshold voltage being less than the first data state threshold voltage and greater than the second data state threshold voltage.