US 11,721,396 B2
Configuration of a memory device for programming memory cells
Violante Moschiano, Avezzano (IT); Purval S. Sule, Folsom, CA (US); Han Liu, Sunnyvale, CA (US); Andrea D'Alessandro, L'Aquila (IT); Pranav Kalavade, San Jose, CA (US); Han Zhao, Santa Clara, CA (US); and Shantanu Rajwade, Sunnyvale, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Sep. 4, 2020, as Appl. No. 17/12,442.
Application 17/012,442 is a continuation of application No. 16/655,826, filed on Oct. 17, 2019, granted, now 10,777,277.
Application 16/655,826 is a continuation of application No. 16/106,185, filed on Aug. 21, 2018, granted, now 10,482,974, issued on Nov. 19, 2019.
Prior Publication US 2020/0402586 A1, Dec. 24, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/12 (2006.01); G11C 11/4074 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 5/06 (2006.01)
CPC G11C 16/12 (2013.01) [G11C 5/063 (2013.01); G11C 11/4074 (2013.01); G11C 16/0483 (2013.01); G11C 16/3427 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory, comprising:
an array of memory cells; and
a controller for access of the array of memory cells;
wherein, during a programming operation on the array of memory cells, the controller is configured to cause the memory to:
apply a first voltage level to a data line selectively connected to a memory cell of the array of memory cells that is selected for the programming operation;
apply a second voltage level, lower than the first voltage level, to a control gate of a select gate connected between the data line and the memory cell selected for the programming operation while continuing to apply the first voltage level to the data line;
decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the control gate of the select gate;
after the voltage level of the data line settles to the third voltage level, increase the voltage level applied to the control gate of the select gate from the second voltage level to a fourth voltage level, higher than the third voltage level, while continuing to apply the third voltage level to the data line; and
after increasing the voltage level applied to the control gate of the select gate to the fourth voltage level, apply a programming voltage to a control gate of the memory cell selected for the programming operation.