US 11,721,395 B2
Timing parameter adjustment mechanisms
Marco Sforzin, Cernusco sul Naviglio (IT); and Daniele Balluchi, Cernusco sul Naviglio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 3, 2021, as Appl. No. 17/518,176.
Application 17/518,176 is a continuation of application No. 16/942,568, filed on Jul. 29, 2020, granted, now 11,183,248.
Prior Publication US 2022/0130461 A1, Apr. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/34 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/30 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory array; and
a controller coupled with the memory array and configured to cause the apparatus to:
receive an access command to access a block of data;
determine a timing parameter associated with a first time to access the block of data and a second time to access the block of data based at least in part on receiving the access command; and
perform an access operation on the block of data based at least in part on the timing parameter.