US 11,721,385 B2
Dynamic power distribution for stacked memory
Anthony D. Veches, Boise, ID (US); and Brian P. Callaway, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 12, 2021, as Appl. No. 17/400,886.
Prior Publication US 2023/0048317 A1, Feb. 16, 2023
Int. Cl. G11C 11/40 (2006.01); G11C 11/4074 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01)
CPC G11C 11/4074 (2013.01) [H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1436 (2013.01)] 31 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a signal at a first semiconductor die, the first semiconductor die comprising circuitry associated with a first memory array and comprising a conductor coupling a power source with a second semiconductor die, the second semiconductor die comprising circuitry associated with a second memory array, wherein the signal comprises an indication of a condition of operating the circuitry associated with the second memory array; and
modifying, based at least in part on receiving the signal, a state of a switching component between the conductor and the circuitry associated with the first memory array.