US 11,721,382 B2
Refresh circuit and memory
Xian Fan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Filed on Feb. 9, 2022, as Appl. No. 17/650,516.
Application 17/650,516 is a continuation of application No. PCT/CN2021/112877, filed on Aug. 16, 2021.
Claims priority of application No. 202011217665.X (CN), filed on Nov. 4, 2020.
Prior Publication US 2022/0270669 A1, Aug. 25, 2022
Int. Cl. G11C 11/406 (2006.01); G11C 7/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01); G11C 29/00 (2006.01)
CPC G11C 11/40611 (2013.01) [G11C 7/1039 (2013.01); G11C 11/4085 (2013.01); G11C 11/4096 (2013.01); G11C 29/785 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A refresh circuit, comprising:
a signal selector, configured to select one of a normal word line logical address and a redundant word line logical address as an output, an output signal of which is designated as a first logical address;
a row address latch, connected to an output terminal of the signal selector and configured to output a row hammer address and a row hammer flag signal according to the first logical address;
a seed arithmetic unit, connected to an output terminal of the row address latch and configured to receive a refresh signal as an excitation signal and generate a seed address according to the row hammer address;
a logical arithmetic unit, connected to an output terminal of the seed arithmetic unit and configured to obtain a row hammer refresh address according to the seed address, wherein the row hammer refresh address is an adjacent physical address of the seed address; and
a pre-decode unit, connected to an output terminal of the logical arithmetic unit and configured to receive the row hammer refresh address, and convert the row hammer refresh address into a physical address to be used by a memory array of a memory to perform a refresh operation.