US 11,721,275 B2
Optimized display image rendering
Atsuo Kuwahara, Hillsboro, OR (US); Deepak S. Vembar, Portland, OR (US); Paul S. Diefenbaugh, Portland, OR (US); Vallabhajosyula S. Somayazulu, Portland, OR (US); and Kofi C. Whitney, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 23, 2022, as Appl. No. 17/993,614.
Application 17/993,614 is a continuation of application No. 17/561,661, filed on Dec. 23, 2021, granted, now 11,514,839.
Application 17/561,661 is a continuation of application No. 17/133,265, filed on Dec. 23, 2020, granted, now 11,210,993, issued on Dec. 28, 2021.
Application 17/133,265 is a continuation of application No. 15/675,653, filed on Aug. 11, 2017, granted, now 11,017,712, issued on May 25, 2021.
Claims priority of provisional application 62/374,696, filed on Aug. 12, 2016.
Prior Publication US 2023/0110339 A1, Apr. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/12 (2006.01); G09G 3/20 (2006.01); G06F 3/01 (2006.01); G06F 3/147 (2006.01)
CPC G09G 3/2096 (2013.01) [G06F 3/012 (2013.01); G06F 3/147 (2013.01); G09G 2320/028 (2013.01); G09G 2320/0252 (2013.01); G09G 2320/0261 (2013.01); G09G 2320/106 (2013.01); G09G 2354/00 (2013.01); G09G 2360/12 (2013.01); G09G 2370/022 (2013.01); G09G 2370/16 (2013.01)] 28 Claims
OG exemplary drawing
 
1. An apparatus comprising:
network interface circuitry;
memory;
instructions; and
processor circuitry to execute the instructions to:
determine a latency, the latency based on a time to display a rendered image;
determine a future user pose at a prediction interval, wherein the future user pose is based on input data, wherein the input data includes a position and an orientation of a user, and wherein the prediction interval is based on the latency;
render an image for display based on the future user pose; and
cause transmission of the rendered image via the network interface circuitry.