CPC G09G 3/2096 (2013.01) [G09G 3/2044 (2013.01); G09G 3/3208 (2013.01); G09G 5/006 (2013.01); G09G 2320/10 (2013.01); G09G 2320/103 (2013.01); G09G 2340/02 (2013.01); G09G 2360/127 (2013.01); G09G 2360/128 (2013.01); G09G 2360/18 (2013.01)] | 19 Claims |
1. A display driving integrated circuit (DDIC) comprising:
a host interface configured to receive image data from a host device;
an interface monitor configured to generate a mode signal indicating:
a video mode in response to detecting a transfer of image data from the host device through the host interface, and
a still image mode in response to detecting an absence of the image data from the host device through the host interface for more than a predetermined non-zero time;
a processing circuit configured to generate processed data by processing the image data;
a conversion circuit configured to perform data conversion on the processed data to generate display data driving a display panel; and
a path controller configured to:
store the processed data in a frame buffer and transfer the processed data stored in the frame buffer to the conversion circuit in response to the mode signal indicating the still image mode, and
transfer the processed data to the conversion circuit without storing the processed data in the frame buffer in response to the mode signal indicating the video mode.
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