CPC G09G 3/2092 (2013.01) [G09G 2310/0278 (2013.01); G09G 2330/028 (2013.01)] | 13 Claims |
1. A gate driver comprising:
a stage including a first input terminal, a second input terminal, a third input terminal, a first output terminal from which a scan signal and a carry signal are output, and a second output terminal from which an inverted carry signal is output,
wherein the stage further comprises:
an input circuit which controls a voltage of a first node and a voltage of a second node based on a previous carry signal of and a previous inverted carry signal supplied from a previous stage, and a signal supplied to the second input terminal; and
an output circuit which outputs the scan signal, the carry signal and the inverted carry signal based on the voltage of the first node and the voltage of the second node,
wherein a signal supplied to the third input terminal is a signal shifted from the signal supplied to the second input terminal.
|