US 11,721,265 B1
Data driving circuit and display device including the same
Hyung Gun Ma, Yongin-si (KR); Gyu Wan Lim, Daejeon (KR); Gyeong Gu Kang, Daejeon (KR); Hyun Sik Kim, Daejeon (KR); Keum Dong Jung, Yongin-si (KR); and Moon Jae Jeong, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Gyeonggi-do (KR); and KOREAN ADVANCE INSTITUTE OF SCIENCE AND TECHNOLOGY, Daejeon (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR); and KOREAN ADVANCE INSTITUTE OF SCIENCE AND TECHNOLOGY, Daejeon (KR)
Filed on Nov. 11, 2022, as Appl. No. 17/985,554.
Claims priority of application No. 10-2022-0021107 (KR), filed on Feb. 17, 2022.
Int. Cl. G09G 3/20 (2006.01); G06F 3/044 (2006.01); G09G 3/3208 (2016.01); H10K 59/40 (2023.01)
CPC G09G 3/20 (2013.01) [G06F 3/044 (2013.01); G09G 3/3208 (2013.01); G09G 2300/0828 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0871 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0291 (2013.01); G09G 2330/028 (2013.01); H10K 59/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A data driving circuit comprising:
a resistor string in which a plurality of resistors are connected in series; and
a plurality of data channels connected to a high voltage node, intermediate voltage nodes, and a low voltage node of the resistor string and configured to convert a digital data signal into an analog data voltage,
wherein each of the plurality of data channels comprises:
a main digital-to-analog converter connected to the high voltage node, the intermediate voltage nodes, and the low voltage node;
a multiplier connected to an output terminal of the main digital-to-analog converter;
a sub digital-to-analog converter connected to some of the high voltage node, the intermediate voltage nodes, and the low voltage node; and
a voltage synthesizer connected to an output terminal of the multiplier and an output terminal of the sub digital-to-analog converter.