US 11,721,048 B2
Image processing apparatus and method
Ohji Nakagami, Tokyo (JP); Koji Yano, Tokyo (JP); Satoru Kuma, Tokyo (JP); and Tsuyoshi Kato, Kanagawa (JP)
Assigned to SONY CORPORATION, Tokyo (JP)
Appl. No. 16/960,910
Filed by Sony Corporation, Tokyo (JP)
PCT Filed Jan. 7, 2019, PCT No. PCT/JP2019/000051
§ 371(c)(1), (2) Date Jul. 9, 2020,
PCT Pub. No. WO2019/142666, PCT Pub. Date Jul. 25, 2019.
Claims priority of application No. 2018-004983 (JP), filed on Jan. 16, 2018.
Prior Publication US 2021/0174559 A1, Jun. 10, 2021
Int. Cl. G06K 9/00 (2022.01); G06T 11/00 (2006.01); G06T 7/50 (2017.01); G06T 9/00 (2006.01)
CPC G06T 11/003 (2013.01) [G06T 7/50 (2017.01); G06T 9/00 (2013.01); G06T 2207/10028 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An image encoding apparatus, comprising:
circuitry configured to:
define a bounding box containing 3D data;
project positional data of the 3D data to at least three 2D layers in a depthwise direction of the bounding box, wherein depth values of the 2D layers are different from each other in the depthwise direction;
encode the projected positional data; and
generate a bit stream including the encoded positional data and signal information representing the number of the 2D layers.