US 11,720,735 B2
Flat shell for an accelerator card
Sebastian Turullols, Los Altos, CA (US); Kyle Corbett, Campbell, CA (US); Sudipto Chakraborty, Longmont, CO (US); Siva Santosh Kumar Pyla, Hyderabad (IN); Ravinder Sharma, Hyderabad (IN); Kaustuv Manji, Hyderabad (IN); Jayaram Pvss, Hyderabad (IN); Stephen P. Rozum, Loveland, CO (US); Ch Vamshi Krishna, Hyderabad (IN); and Susheel Puthana, Longmont, CO (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Aug. 20, 2021, as Appl. No. 17/408,218.
Prior Publication US 2023/0055704 A1, Feb. 23, 2023
Int. Cl. G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/3953 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/398 (2020.01); G06F 30/3953 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry;
synthesizing, using the computer hardware, a kernel specifying user circuitry, wherein the kernel is obtained from the one or more computer readable storage media;
linking, using the computer hardware, the synthesized kernel to the flat shell forming a unified circuit design; and
using the computer hardware, placing and routing the unified circuit design to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.