US 11,720,728 B1
Version tracking and control for integrated circuit design
Joseph Cascioli, Ithaca, NY (US)
Assigned to ARCHITECTURE TECHNOLOGY CORPORATION, Eden Prairie, MN (US)
Filed by ARCHITECTURE TECHNOLOGY CORPORATION, Eden Prairie, MN (US)
Filed on Sep. 20, 2021, as Appl. No. 17/480,069.
Application 17/480,069 is a continuation of application No. 16/983,727, filed on Aug. 3, 2020, granted, now 11,126,767.
Application 16/983,727 is a continuation of application No. 16/367,006, filed on Mar. 27, 2019, granted, now 10,733,341, issued on Aug. 4, 2020.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/30 (2020.01); H04L 9/08 (2006.01)
CPC G06F 30/30 (2020.01) [H04L 9/0819 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
generating, by a computer, a multi-dimensional distributed ledger for an integrated circuit (IC) design defined by hardware description language code, the multi-dimensional distributed ledger having a first chain in a first direction and a second chain in a second direction;
detecting, by the computer, a code differential in the hardware description language code defining the IC design;
appending, by the computer, a first digital block containing the code differential to the first chain in the first direction of the multi-dimensional distributed ledger;
generating, by the computer, a data record based upon a simulation of the IC design using the hardware description language code with the code differential; and
appending, by the computer, a second digital block containing the data record to the second chain in the second direction of the multi-dimensional distributed ledger.