US 11,720,672 B2
Method, system and apparatus for error correction coding embedded in physically unclonable function arrays
Kuan-Yueh Shen, Portland, OR (US); David Johnston, Hillsboro, OR (US); Rachael J. Parker, Forest Grove, OR (US); and Javier Dacuna Santos, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 25, 2022, as Appl. No. 17/728,907.
Application 17/728,907 is a continuation of application No. 16/234,348, filed on Dec. 27, 2018, granted, now 11,321,459.
Prior Publication US 2022/0253525 A1, Aug. 11, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 21/55 (2013.01); G06F 11/10 (2006.01); H04L 9/32 (2006.01); H04L 9/08 (2006.01); G06F 7/58 (2006.01); G06F 21/00 (2013.01)
CPC G06F 21/556 (2013.01) [G06F 7/588 (2013.01); G06F 11/1076 (2013.01); G06F 21/00 (2013.01); H04L 9/0866 (2013.01); H04L 9/0894 (2013.01); H04L 9/3278 (2013.01); G06F 2221/034 (2013.01); H04L 2209/34 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A Physically Unclonable Function (PUF) circuit array, comprising:
a plurality of first data bits and a plurality of second data bits;
a write circuitry configured to store a plurality of first data bits into a respective ones of the plurality of first bitcells and to store a plurality of second data bits to a respective ones of the plurality of second bitcells, the plurality of first data bits defining a first dataset and the plurality of second data bits defining a helper dataset; and
a parity bit array configured to read the helper dataset from the plurality of second bitcells and to apply an error correction factor as a function of the helper data to the first read dataset to form a security key dataset;
wherein the first, dataset and the second dataset are dispersedly stored on the PUF circuit array such that its identity of the stored data as the first dataset or the second data set is unknowable.