US 11,720,499 B2
Selective generation of miss requests for cache lines
Fataneh Ghodrat, Boxborough, MA (US); Stephen W. Somogyi, Boxborough, MA (US); and Zhenhong Liu, Santa Clara, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US); and SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 28, 2020, as Appl. No. 17/134,790.
Prior Publication US 2022/0206950 A1, Jun. 30, 2022
Int. Cl. G06F 12/0891 (2016.01); G06T 1/60 (2006.01); G06T 1/20 (2006.01); G06F 12/0831 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 12/0833 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a texture cache comprising cache lines that are partitioned into a plurality of subsets; and
at least one compute unit in a graphics pipeline, wherein the compute unit is configured to selectively generate a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to:
a cache miss for a memory access request to an address associated with the first subset of the cache line; and
a characteristic of data stored at the cache line, the characteristic indicating whether color compression or depth compression is enabled.