US 11,720,495 B2
Multi-level cache security
Abhijeet Ashok Chachad, Plano, TX (US); David Matthew Thompson, Dallas, TX (US); and Naveen Bhoria, Plano, TX (US)
Assigned to Texas Instmments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on May 22, 2020, as Appl. No. 16/882,380.
Claims priority of provisional application 62/852,468, filed on May 24, 2019.
Prior Publication US 2020/0371927 A1, Nov. 26, 2020
Int. Cl. G06F 12/0811 (2016.01); G06F 9/46 (2006.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/1081 (2016.01); G06F 12/14 (2006.01); G06F 21/79 (2013.01); G06F 12/128 (2016.01); G06F 12/0864 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 9/467 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/1081 (2013.01); G06F 12/1441 (2013.01); G06F 21/79 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a central processing unit (CPU) arranged to execute program instructions to manipulate data in at least a first or second secure context, wherein the first and second secure contexts indicate different levels of security;
a first level cache coupled to the CPU to temporarily store data in cache lines for manipulation by the CPU, wherein the first level cache includes a first secure code memory for storing a first-level-cache secure code list of secure codes, wherein each secure code indicates one of the at least first or second secure contexts by which data for a respective cache line is received, and wherein the first level cache includes a first level cache controller; and
a second level cache coupled to the first level cache to temporarily store data in cache lines for manipulation by the CPU, wherein the second level cache includes a second secure code memory for storing a second-level-cache secure code list of secure codes, wherein each secure code indicates one of the at least first or second secure contexts by which data for a respective cache line is received, and wherein the second level cache includes a second level cache controller;
wherein the first level cache controller is configured to send an access request to the second level cache controller, the access request including an address of a selected cache line of data and a secure code indicating the one of the at least first or second secure contexts by which data for the selected cache line was received; and
wherein the second level cache controller is configured to compare the address and the secure code of the access request against a secure code stored in the second level cache for a cache line of data indicated by the address of the access request, and in response to the comparison, execute a cache coherency operation.