US 11,720,493 B2
Cache management based on memory device over-provisioning
Kevin R. Brandt, Boise, ID (US); Peter Feeley, Boise, ID (US); Kishore Kumar Muchherla, Fremont, CA (US); Yun Li, Fremont, CA (US); Sampath K. Ratnam, Boise, ID (US); Ashutosh Malshe, Fremont, CA (US); Christopher S. Hale, Boise, ID (US); and Daniel J. Hubbard, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 21, 2022, as Appl. No. 17/581,108.
Application 17/581,108 is a continuation of application No. 17/097,477, filed on Nov. 13, 2020, granted, now 11,256,620.
Prior Publication US 2022/0156187 A1, May 19, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
determining, by a processing device, an amount of valid management units in a memory device of a memory sub-system;
determining a surplus amount of valid management units on the memory device based on a minimum system requirement of valid management units; and
configuring a size of a cache of the memory device based on the surplus amount of valid management units.