US 11,720,490 B2
Managing host input/output in a memory system executing a table flush
Yuehhung Chen, Sunnyvale, CA (US); Chih-Kuo Kao, Fremont, CA (US); Fangfang Zhu, San Jose, CA (US); and Jiangli Zhu, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 31, 2021, as Appl. No. 17/446,519.
Prior Publication US 2023/0069382 A1, Mar. 2, 2023
Int. Cl. G06F 12/02 (2006.01); G06F 12/0891 (2016.01); G06F 3/06 (2006.01)
CPC G06F 12/0292 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 12/0891 (2013.01); G06F 2212/7201 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
responsive to receiving a table flush command,
performing a flush operation on the address mapping table;
responsive to receiving at least one memory access command, suspending the flush operation after a predefined portion of the address mapping table is flushed;
performing at least one memory access operation specified by the at least one memory access command; and
resuming the performance of the flush operation on the address mapping table.