US 11,720,479 B2
Real time analysis and control for a multiprocessor system
Geoffrey N. Ellis, Santa Cruz, CA (US); John Mark Beardslee, Menlo Park, CA (US); Michael B. Doerr, Dripping Springs, TX (US); Ivan Aguayo, Austin, TX (US); and Brian A. Dalio, Keller, TX (US)
Assigned to Coherent Logix, Incorporated, Austin, TX (US)
Filed by Coherent Logix, Incorporated, Austin, TX (US)
Filed on Oct. 17, 2018, as Appl. No. 16/162,558.
Application 16/162,558 is a continuation of application No. 15/276,370, filed on Sep. 26, 2016, granted, now 10,114,739.
Application 15/276,370 is a continuation of application No. 14/074,925, filed on Nov. 8, 2013, granted, now 9,477,585, issued on Oct. 25, 2016.
Claims priority of provisional application 61/724,493, filed on Nov. 9, 2012.
Prior Publication US 2019/0050324 A1, Feb. 14, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/36 (2006.01); G06F 11/22 (2006.01); G06F 30/00 (2020.01); G06F 13/28 (2006.01); G06F 9/455 (2018.01); G06F 30/34 (2020.01)
CPC G06F 11/3688 (2013.01) [G06F 11/2242 (2013.01); G06F 11/3664 (2013.01); G06F 13/28 (2013.01); G06F 30/00 (2020.01); G06F 9/45504 (2013.01); G06F 30/34 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
executing application software using a first hardware resource of a multi-processor array, wherein the multi-processor array includes a plurality of processing elements, a plurality of memories, and an interconnection network communicatively coupling the plurality of processing elements to the plurality of memories, wherein the first hardware resource includes a first subset of the plurality of processing elements;
in response to executing, using a second hardware resource of the multi-processor array, at least one probe command included in test software:
duplicating, by a particular processing element of the plurality of processing elements, a read operation on a portion of a data stream generated in the first hardware resource to generate a duplicate data block that includes a copy of the portion of the data stream;
filtering, by the particular processing element, the duplicate data block to generate a filtered data block;
writing, by the particular processing element, the filtered data block to an unused memory of the plurality of memories; and
generating, by the particular processing element, test results using the filtered data block; and
wherein the second hardware resource includes a second subset of the plurality of processing elements different than the first subset of the plurality of processing elements; and
verifying operation of the application software based on the test results.