US 11,720,475 B2
Debugging dataflow computer architectures
Skyler Arron Windh, McKinney, TX (US); Tony M. Brewer, Plano, TX (US); and Patrick Estep, Rowlett, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 21, 2022, as Appl. No. 17/991,390.
Application 17/991,390 is a continuation of application No. 17/405,211, filed on Aug. 18, 2021, granted, now 11,507,493.
Prior Publication US 2023/0079727 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/44 (2018.01); G06F 11/36 (2006.01); G06F 9/30 (2018.01)
CPC G06F 11/3656 (2013.01) [G06F 9/30189 (2013.01); G06F 11/3644 (2013.01); G06F 11/3664 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
executing a set of instructions in a plurality of processing elements of a coarse grained reconfigurable array (CGRA) of a compute-near-memory system;
detecting, during executing of the set of instructions, a stop condition encountered on a processing element of the plurality of processing elements;
responsive to detecting the stop condition, stopping execution of the set of instruction on the processing element and sending, via the processing element a stop signal to a first set of one or more processing elements of the plurality of processing elements, each processing element in the first set of one or more processing elements sending the stop signal to a second set of one or more processing elements of the plurality of processing elements; and
causing delivery of state information of each of the plurality of processing elements to a software simulator, the state information configured to allow the software simulator to start execution from a point in the set of instructions where the stop condition was detected.