US 11,720,444 B1
Increasing of cache reliability lifetime through dynamic invalidation and deactivation of problematic cache lines
Ofer Naaman, Hod Hasharon (IL); Osnat Katz, Alone Aba (IL); Nir Bar-Or, Hadera (IL); and Adi Habusha, Alonei Abba (IL)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Dec. 10, 2021, as Appl. No. 17/548,190.
Int. Cl. G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01); G06F 12/0891 (2016.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 12/0238 (2013.01); G06F 12/0891 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system of error detection in an integrated circuit, the system comprising:
a cache memory including a plurality of cache memory lines;
error detection logic coupled to the cache memory, the error detection logic including a plurality of outputs, wherein each of the plurality of outputs has a one-to-one correspondence with the plurality of cache memory lines such that one of the plurality of outputs is configured to be activated when an error is detected on a corresponding cache memory line;
a plurality of counters coupled to the plurality of outputs of the error detection logic to count a number of errors for each cache memory line, wherein the plurality of counters includes one counter per each cache memory line;
a plurality of comparators coupled to the plurality of counters for comparing whether each of the plurality of counters reaches a threshold;
a cache line vector coupled to the plurality of comparators, the cache line vector including a plurality of memory elements for storing whether each of the plurality of comparators has reached the threshold; and
a cache controller coupled to the cache line vector and coupled to the cache memory lines for selectively invalidating and deactivating a cache line corresponding to one of the plurality of memory elements in the cache line vector that has reached the threshold.