US 11,720,443 B2
Error correction management for a memory device
Aaron P. Boehm, Boise, ID (US); and Scott E. Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 3, 2021, as Appl. No. 17/518,160.
Application 17/518,160 is a continuation of application No. 16/578,094, filed on Sep. 20, 2019, granted, now 11,182,244.
Claims priority of provisional application 62/746,295, filed on Oct. 16, 2018.
Prior Publication US 2022/0058084 A1, Feb. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G11C 11/409 (2006.01); G06F 12/14 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/102 (2013.01); G06F 11/1016 (2013.01); G06F 12/1425 (2013.01); G11C 11/409 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
switching from operating according to a first mode of operation to operating according to a second mode of operation, wherein the second mode of operation is for testing error correcting functionality;
receiving, from a host device, a first command to write a first set of data;
generating a codeword based at least in part on the first command and the first set of data;
receiving, from the host device, a second command to read the first set of data;
altering the codeword corresponding to the first set of data based at least in part on operating according to the second mode of operation;
transmitting, to the host device, a second set of data different than the first set of data in response to the second command and based at least in part on altering the codeword; and
validating functionality of an operation for error correction based at least in part on the second set of data being different than the first set of data.