US 11,720,442 B2
Memory controller performing selective and parallel error correction, system including the same and operating method of memory device
Hyeokjun Choe, Hwaseong-si (KR); Heehyun Nam, Seoul (KR); Jeongho Lee, Gwacheon-si (KR); and Younho Jeon, Gimhae-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 26, 2021, as Appl. No. 17/510,898.
Claims priority of application No. 10-2020-0154848 (KR), filed on Nov. 18, 2020.
Prior Publication US 2022/0156146 A1, May 19, 2022
Int. Cl. H03M 13/15 (2006.01); G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/0772 (2013.01)] 18 Claims
OG exemplary drawing
 
8. A method performed by a device connected to a host processor via a bus, the method comprising:
receiving a first read request from the host processor;
transmitting the first read request to a memory and reading data corresponding to the first read request from the memory;
detecting an error of read data;
correcting the error included in the read data based on a reference latency or a reference error correction level included in a first error correction option; and
providing first correction data to the host processor,
wherein the correcting of the error included in the read data comprises: according to whether it is possible to satisfy the reference error correction level within the reference latency, correcting the error through a fixed error correction circuit or a variable error correction circuit,
wherein the fixed error correction circuit is configured to correct the read data to an error-free state, and
wherein the variable error correction circuit is configured to correct the read data to satisfy the reference error correction level.