CPC G06F 11/1068 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/0772 (2013.01)] | 18 Claims |
8. A method performed by a device connected to a host processor via a bus, the method comprising:
receiving a first read request from the host processor;
transmitting the first read request to a memory and reading data corresponding to the first read request from the memory;
detecting an error of read data;
correcting the error included in the read data based on a reference latency or a reference error correction level included in a first error correction option; and
providing first correction data to the host processor,
wherein the correcting of the error included in the read data comprises: according to whether it is possible to satisfy the reference error correction level within the reference latency, correcting the error through a fixed error correction circuit or a variable error correction circuit,
wherein the fixed error correction circuit is configured to correct the read data to an error-free state, and
wherein the variable error correction circuit is configured to correct the read data to satisfy the reference error correction level.
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