US 11,720,441 B2
Processing-in-memory (PIM) devices
Jeong Jun Lee, Gwangju-si (KR); and Choung Ki Song, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Aug. 25, 2020, as Appl. No. 17/2,341.
Claims priority of application No. 10-2019-0117098 (KR), filed on Sep. 23, 2019.
Prior Publication US 2021/0089390 A1, Mar. 25, 2021
Int. Cl. G06F 11/10 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01)
CPC G06F 11/1048 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A Processing-In-Memory (PIM) device comprising:
a first storage region configured to store first data;
a second storage region configured to store second data;
an error correction code (ECC) logic circuit comprising a parity and syndrome (parity/syndrome) generator configured to generate a parity for the first data to write the parity into the first storage region during the write operation and configured to generate and output a syndrome for the first data and the parity during the read operation,
wherein the ECC logic circuit is configured to execute an ECC calculation on the first data to generate an error code indicating an error location of the first data, and
wherein the parity/syndrome generator is configured to output the error signal indicating whether an error exists in the first data to the multiplication result compensating circuit in the MAC mode; and
a multiplication and accumulation (MAC) operator configured to execute a MAC calculation on the first data and second data in an MAC mode,
wherein the MAC operator includes;
a multiplying block configured to multiply the first data and the second data to generate multiplication result data;
a multiplication result compensating circuit configured to compensate the multiplication result data based on the error code and the second data; and
an adding block configured to add the compensated multiplication result data, and
wherein the multiplication result compensating circuit outputs the multiplication result data when the error signal indicates that no error exists in the first data.