| CPC G06F 11/079 (2013.01) [G06F 11/0724 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01)] | 9 Claims |
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1. A multi-thread processor, including:
a first processor configured to execute at least a first thread and a second thread;
a second processor configured to execute at least a third thread and a fourth thread;
an instruction execution is initiated in the first thread of the first processor at a first cycle, the execution of the instruction results in a first data to be written to a first storage location;
the instruction execution is initiated in the second thread of the first processor at a second cycle, the execution of the instruction results in a second data to be written to a second storage location;
the instruction execution is initiated in the third thread of the second processor at a third cycle, the execution of the instruction results in a third data to be written to a third storage location;
the instruction execution is initiated in the fourth thread of the second processor at a fourth cycle, the execution of the instruction results in a fourth data to be written to a fourth storage location; and
at least one data compare engine configured to selectively compare the first data, the second date, the third data and the fourth data to detect an error in execution of the instruction by one or more of the first thread, the second thread, the third thread, and the fourth thread, wherein the first storage location and the second storage location are the same, the third storage location and the fourth storage location are the same and a first storage write delay circuit configured to selectively hold the second data, and a second storage write delay circuit configured to hold the fourth data so as to permit a first data compare engine to selectively compare the first data, the second data, the third data and the fourth data prior to the second data overwriting the first data and the fourth data overwriting the third data.
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