US 11,720,422 B1
Unified container for hardware and software binaries
Hem C. Neema, San Jose, CA (US); Sonal Santan, San Jose, CA (US); Soren T. Soe, San Jose, CA (US); Stephen P. Rozum, Loveland, CO (US); and Nik Cimino, Frederick, CO (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Mar. 11, 2021, as Appl. No. 17/198,887.
Application 17/198,887 is a continuation of application No. 15/848,691, filed on Dec. 20, 2017, granted, now 10,956,241.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/54 (2006.01); G06F 21/53 (2013.01); G06F 8/41 (2018.01); G06F 21/57 (2013.01); G06F 8/65 (2018.01)
CPC G06F 9/545 (2013.01) [G06F 8/44 (2013.01); G06F 21/53 (2013.01); G06F 21/572 (2013.01); G06F 8/65 (2013.01)] 18 Claims
OG exemplary drawing
 
10. A system, comprising:
a processor programmed to initiate operations including:
selecting a unified container file, wherein the unified container file includes a plurality of files embedded therein that are used to configure a programmable integrated circuit;
wherein the plurality of files includes a first partial configuration bitstream and a second partial configuration bitstream;
wherein the unified container file includes metadata specifying a defined relationship between the first partial configuration bitstream and the second partial configuration bitstream for programming the programmable integrated circuit;
determining the defined relationship by reading the metadata from the unified container file; and
configuring the programmable integrated circuit based on the defined relationship specified by the metadata using the first partial configuration bitstream and the second partial configuration bitstream;
wherein the defined relationship includes a dependency between the first partial configuration bitstream and the second partial configuration bitstream.