US 11,720,405 B2
Accelerator, method of operating the same, and electronic device including the same
Wookeun Jung, Seoul (KR); Jaejin Lee, Seoul (KR); and Seung Wook Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR); and Seoul National University R&DB Foundation, Seoul (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR); and Seoul National University R&DB Foundation, Seoul (KR)
Filed on Jan. 11, 2021, as Appl. No. 17/145,958.
Claims priority of application No. 10-2020-0075682 (KR), filed on Jun. 22, 2020.
Prior Publication US 2021/0397481 A1, Dec. 23, 2021
Int. Cl. G06F 9/38 (2018.01); G06N 3/063 (2023.01); G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 9/30 (2018.01)
CPC G06F 9/5027 (2013.01) [G06F 9/30014 (2013.01); G06F 9/3802 (2013.01); G06F 9/3836 (2013.01); G06F 9/48 (2013.01); G06N 3/063 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A processor-implemented accelerator method, the method comprising:
reading, from a memory, an instruction to be executed in an accelerator, the instruction embedding a parameter value of at least some portion of layers in a neural network for an inference task;
reading, from the memory, input data based on the instruction;
reading, from the instruction, the parameter value for the inference task; and
performing, on the input data and the parameter value embedded in the instruction, the inference task instructed by the instruction.