US 11,720,355 B2
Instructions and logic to perform floating point and integer operations for machine learning
Himanshu Kaul, Portland, OR (US); Mark A. Anders, Hillsboro, OR (US); Sanu K. Mathew, Hillsboro, OR (US); Anbang Yao, Beijing (CN); Joydeep Ray, Folsom, CA (US); Ping T. Tang, Edison, NJ (US); Michael S. Strickland, Sunnyvale, CA (US); Xiaoming Chen, Shanghai (CN); Tatiana Shpeisman, Menlo Park, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Altug Koker, El Dorado Hills, CA (US); Kamal Sinha, Rancho Cordova, CA (US); Balaji Vembu, Folsom, CA (US); Nicolas C. Galoppo Von Borries, Portland, OR (US); Eriko Nurvitadhi, Hillsboro, OR (US); Rajkishore Barik, Santa Clara, CA (US); Tsung-Han Lin, Campbell, CA (US); Vasanth Ranganathan, El Dorado Hills, CA (US); and Sanjeev Jahagirdar, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 7, 2022, as Appl. No. 17/834,482.
Application 17/834,482 is a continuation of application No. 17/305,355, filed on Jul. 6, 2021, granted, now 11,360,767.
Application 17/305,355 is a continuation of application No. 17/169,232, filed on Feb. 5, 2021, granted, now 11,080,046, issued on Aug. 3, 2021.
Application 17/169,232 is a continuation of application No. 17/115,989, filed on Dec. 9, 2020.
Application 17/115,989 is a continuation of application No. 16/432,402, filed on Jun. 5, 2019, granted, now 11,169,799, issued on Nov. 9, 2021.
Application 16/432,402 is a continuation of application No. 15/819,152, filed on Nov. 21, 2017, granted, now 10,353,706, issued on Jul. 16, 2019.
Application 15/819,152 is a continuation of application No. 15/787,129, filed on Oct. 18, 2017, granted, now 10,474,458, issued on Nov. 12, 2019.
Claims priority of provisional application 62/491,699, filed on Apr. 28, 2017.
Prior Publication US 2022/0357945 A1, Nov. 10, 2022
Int. Cl. G06F 9/30 (2018.01); G09G 5/393 (2006.01); G06F 9/38 (2018.01); G06F 7/483 (2006.01); G06F 7/544 (2006.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06T 15/00 (2011.01); G06N 20/00 (2019.01); G06F 17/16 (2006.01)
CPC G06F 9/3001 (2013.01) [G06F 7/483 (2013.01); G06F 7/5443 (2013.01); G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/3851 (2013.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G09G 5/393 (2013.01); G06F 9/3013 (2013.01); G06F 9/30025 (2013.01); G06F 17/16 (2013.01); G06F 2207/3824 (2013.01); G06N 20/00 (2019.01); G06T 15/005 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A graphics processor comprising:
a memory controller; and
a graphics multiprocessor coupled with the memory controller, the graphics multiprocessor including first circuitry configured to:
execute an instruction to perform a matrix operation on first input and second input;
generate intermediate data based on a result of the matrix operation;
convert the intermediate data to a floating-point format determined based on statistics associated with first output data; and
output, as second output data, converted intermediate data in a determined floating-point format.