US 11,720,328 B2
Processing unit with small footprint arithmetic logic unit
Bin He, Orlando, FL (US); Shubh Shah, Santa Clara, CA (US); and Michael Mantor, Orlando, FL (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Sep. 23, 2020, as Appl. No. 17/29,836.
Claims priority of provisional application 63/044,544, filed on Jun. 26, 2020.
Prior Publication US 2021/0405968 A1, Dec. 30, 2021
Int. Cl. G06F 7/57 (2006.01); G06N 3/08 (2023.01); G06F 17/16 (2006.01)
CPC G06F 7/57 (2013.01) [G06F 17/16 (2013.01); G06N 3/08 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method comprising:
in response to an instruction, executing at an arithmetic logic unit (ALU) of a processing unit a plurality of mathematical operations, using a plurality of operands, via a corresponding plurality of stages of the ALU;
reducing a first operand of the plurality of operands between a first stage and a second stage of the plurality of stages, wherein reducing the first operand includes discarding at least a portion of the first operand; and
reducing a second operand of the plurality of operands between the first stage and the second stage of the plurality of stages, wherein reducing the second operand includes discarding at least a portion of the second operand, wherein the discarded portion of the first operand is of a different size than the discarded portion of the second operand.