CPC G06F 7/57 (2013.01) [G06F 17/16 (2013.01); G06N 3/08 (2013.01)] | 17 Claims |
1. A method comprising:
in response to an instruction, executing at an arithmetic logic unit (ALU) of a processing unit a plurality of mathematical operations, using a plurality of operands, via a corresponding plurality of stages of the ALU;
reducing a first operand of the plurality of operands between a first stage and a second stage of the plurality of stages, wherein reducing the first operand includes discarding at least a portion of the first operand; and
reducing a second operand of the plurality of operands between the first stage and the second stage of the plurality of stages, wherein reducing the second operand includes discarding at least a portion of the second operand, wherein the discarded portion of the first operand is of a different size than the discarded portion of the second operand.
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