CPC G06F 3/0659 (2013.01) [G06F 3/067 (2013.01); G06F 3/0619 (2013.01); G06F 3/0631 (2013.01); G06F 3/0656 (2013.01)] | 20 Claims |
1. A double data rate (“DDR”) controller system comprising:
a plurality of read data buffers, wherein each of the plurality of read data buffers is configured for read data storage;
a port read response queue that stores information corresponding to an incoming read;
a command queue configured to receive read data buffer state information from the port read response queue by way of a read data buffer allocation tracker; and
said read data buffer allocation tracker configured to track said read data buffer state information of each of the plurality of read data buffers.
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