US 11,720,284 B2
Low latency storage based on data size
Federica Cresci, Milan (IT); Nicola Del Gatto, Cassina de' Pecchi (IT); Massimiliano Patriarca, Milan (IT); Maddalena Calzolari, Milan (IT); Michela Spagnolo, Sesto San Giovanni (IT); and Massimiliano Turconi, Gorgonzola (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 29, 2021, as Appl. No. 17/244,734.
Prior Publication US 2022/0350533 A1, Nov. 3, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01)] 26 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory;
logic configured to receive a command from a host; and
a processor coupled with the memory and the logic, the processor configured to:
determine, based at least in part on the command, that data to be accessed is smaller than a threshold;
write, to the memory, data associated with the command based at least in part on the determining, wherein the logic is further configured to read, from the memory, the data based at least in part on an indication from the processor that the data has been written to the memory, and to output the data to the host; and
send, to the logic, a second command comprising the indication based at least in part on writing the data to the memory.