US 11,720,283 B2
Coherent access to persistent memory region range
Shay Benisty, Beer Sheva (IL); Ariel Navon, Revava (IL); and Judah Gamliel Hahn, Ofra (IL)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Feb. 18, 2021, as Appl. No. 17/178,770.
Application 17/178,770 is a continuation in part of application No. 15/847,671, filed on Dec. 19, 2017, granted, now 10,929,309, issued on Feb. 23, 2021.
Prior Publication US 2021/0173589 A1, Jun. 10, 2021
Int. Cl. G06F 3/06 (2006.01); G06F 9/48 (2006.01); G06F 12/1081 (2016.01); G06F 9/30 (2018.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 3/0679 (2013.01); G06F 9/30043 (2013.01); G06F 9/4881 (2013.01); G06F 12/1081 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A data storage device, comprising:
a controller configured to execute a method of driver access and driverless access of a non-volatile memory of a non-volatile memory device by a host, the method comprising:
initializing a Peripheral Component Interconnect express (PCIe) memory space configured to map a portion of the non-volatile memory of the non-volatile memory device to a host memory space through a PCIe link between the host and the non-volatile memory device;
initializing a PCIe configuration space with configuration information of the non-volatile memory device;
sending load/store commands to a persistent memory region (PMR) queue of the PCIe memory space for driverless access;
sending read/write commands to a Non-Volatile Memory express (NVMe) driver of the host for driver access utilizing the configuration information of the non-volatile memory device; and
aggregating the load/store commands and the read/write commands in an aggregated command queue for processing by the non-volatile memory device.