US 11,720,273 B2
Codeword error leveling for 3DXP memory devices
Jian Huang, Union City, CA (US); Zhenming Zhou, San Jose, CA (US); and Zhenlei Shen, Milpitas, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 18, 2021, as Appl. No. 17/323,089.
Prior Publication US 2022/0374157 A1, Nov. 24, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01)
CPC G06F 3/0644 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0688 (2013.01); G06F 11/076 (2013.01); G06F 11/0727 (2013.01)] 20 Claims
OG exemplary drawing
 
8. A method comprising:
identifying, by a processing device, a plurality of partitions located on a die of a memory device;
selecting, based on evaluating a predefined criterion reflecting a physical layout of the die of the memory device, a first partition and a second partition of the plurality of partitions, wherein the evaluating is based on a physical address of the first partition and a physical address of the second partition; and
generating a codeword comprising first data residing on the first partition and second data residing on the second partition.