US 11,720,258 B2
Memory bypass for error detection and correction
Chinnakrishnan Ballapuram, San Jose, CA (US); Saira S. Malik, Lafayette, IN (US); and Taeksang Song, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 16, 2021, as Appl. No. 17/349,626.
Claims priority of provisional application 63/046,876, filed on Jul. 1, 2020.
Prior Publication US 2022/0004324 A1, Jan. 6, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0673 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array; and
a control component coupled with the memory array and configured to cause the apparatus to:
receive, from a host device, a read command associated with reading data from the memory array;
read the data from a bank of the memory array based at least in part on the read command;
transmit, to the host device concurrently with transmitting a first portion of the data to the host device and before transmitting a second portion of the data, an indication of an error status of the first portion of the data;
determine whether there is an error in a second portion of the data; and
transmit, after transmitting the indication of the error status and the first portion of the data and concurrently with transmitting the second portion of the data to the host device, an alert to the host device that there is the error in the second portion of the data.