CPC G06F 3/0608 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
1. A digital circuit comprising:
memory, the memory storing data comprising a plurality of digital values, wherein N non-zero digital values are stored in a block, where N is a first integer, the N non-zero digital values being associated with a first bit mask specifying positions of the N non-zero digital values;
a decompression circuit to receive the N non-zero digital values and the first bit mask and produce two N length sets of digital values from the N non-zero digital values, wherein positions of the non-zero digital values in each of the two N length sets of digital values are set based on the first bit mask; and
a processor to receive the two N length sets of digital values and two second bit masks, and process the two N length sets of digital values using the two second bit masks.
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