US 11,720,248 B2
Configurable cache for multi-endpoint heterogeneous coherent system
Kai Chirca, Dallas, TX (US); and Matthew David Pierson, Frisco, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Apr. 6, 2022, as Appl. No. 17/715,022.
Application 17/715,022 is a continuation of application No. 16/653,263, filed on Oct. 15, 2019, granted, now 11,307,988.
Claims priority of provisional application 62/745,842, filed on Oct. 15, 2018.
Prior Publication US 2022/0229779 A1, Jul. 21, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/084 (2016.01); G06F 12/0811 (2016.01); G06F 12/1009 (2016.01); G06F 12/0875 (2016.01); G06F 12/10 (2016.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 12/0855 (2016.01); G06F 12/06 (2006.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 13/12 (2006.01); G06F 12/0815 (2016.01); H03M 13/01 (2006.01); H03M 13/09 (2006.01); H03M 13/15 (2006.01); H03M 13/27 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 12/0891 (2016.01); G06F 12/0846 (2016.01); G06F 12/0862 (2016.01)
CPC G06F 3/0604 (2013.01) [G06F 3/064 (2013.01); G06F 3/0607 (2013.01); G06F 3/0632 (2013.01); G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 9/30101 (2013.01); G06F 9/30123 (2013.01); G06F 9/3897 (2013.01); G06F 9/4881 (2013.01); G06F 9/5016 (2013.01); G06F 12/0607 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/0855 (2013.01); G06F 12/0857 (2013.01); G06F 12/0875 (2013.01); G06F 12/0891 (2013.01); G06F 12/10 (2013.01); G06F 12/1009 (2013.01); G06F 13/124 (2013.01); G06F 13/1642 (2013.01); G06F 13/1663 (2013.01); G06F 13/1668 (2013.01); G06F 13/4027 (2013.01); H03M 13/015 (2013.01); H03M 13/098 (2013.01); H03M 13/1575 (2013.01); H03M 13/276 (2013.01); H03M 13/2785 (2013.01); G06F 12/0833 (2013.01); G06F 12/0846 (2013.01); G06F 12/0851 (2013.01); G06F 12/0862 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1048 (2013.01); G06F 2212/304 (2013.01); G06F 2212/452 (2013.01); G06F 2212/6024 (2013.01); G06F 2212/657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a cache configuration register; and
a controller coupled to the cache configuration register, the controller configured to:
receive a random allocation pointer;
retrieve an AND mask from the cache configuration register;
retrieve an OR mask from the cache configuration register;
perform a first AND operation with a first bit of the random allocation pointer and a first AND mask bit to generate a first output bit;
perform a second AND operation with a second bit of the random allocation pointer and a second AND mask bit to generate a second output bit;
perform a first OR operation with the first output bit and a first OR mask bit to generate a first way identifier bit; and
perform a second OR operation with the second output bit and a second OR mask bit to generate a second way identifier bit.