US 11,720,158 B2
Power throttling mechanism using instruction rate limiting in high power machine-learning ASICs
Houle Gan, Santa Clara, CA (US); Thomas James Norrie, Mountain View, CA (US); Gregory Sizikov, Sunnyvale,, CA (US); and Georgios Konstadinidis, San Jose, CA (US)
Assigned to Google LLC, Mountain View, CA (US)
Filed by Google LLC, Mountain View, CA (US)
Filed on Mar. 13, 2020, as Appl. No. 16/818,493.
Prior Publication US 2021/0286419 A1, Sep. 16, 2021
Int. Cl. G06F 1/28 (2006.01); G06N 20/00 (2019.01)
CPC G06F 1/28 (2013.01) [G06N 20/00 (2019.01)] 14 Claims
OG exemplary drawing
 
1. A method of regulating power usage of an integrated circuit (IC) comprising:
measuring, by a voltage regulator, a current load;
determining, by the voltage regulator, that the current load satisfies a threshold level indicating an over current condition;
providing, by the voltage regulator, a signal indicating the over current condition to a synchronizer of the IC;
synchronizing, by the synchronizer, the signal to an internal clock domain of the IC to produce a synchronized signal in phase with the internal clock of the IC;
providing, by the synchronizer, the synchronized signal to a sequencer of the IC, the sequencer controlling a flow of instructions to be processed by the IC; and
reducing, by the sequencer in response to the synchronized signal, the flow of instructions to be processed by one or more processors in the IC to limit a processing rate of the IC according to a throttling mask, the throttling masking limiting a rate of data to be processed by the one or more processors in the IC.