US 11,720,136 B2
Controllable temperature coefficient bias circuit
Robert Mark Englekirk, Littleton, CO (US); Keith Bargroff, San Diego, CA (US); Christopher C. Murphy, Lake Zurich, IL (US); and Tero Tapio Ranta, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Nov. 15, 2022, as Appl. No. 17/987,722.
Application 17/987,722 is a continuation of application No. 16/989,435, filed on Aug. 10, 2020, granted, now 11,507,125.
Application 16/989,435 is a continuation of application No. 15/793,943, filed on Oct. 25, 2017, granted, now 10,775,827, issued on Sep. 15, 2020.
Prior Publication US 2023/0152836 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G05F 3/26 (2006.01); H03M 1/66 (2006.01); G05F 3/24 (2006.01); H03M 1/74 (2006.01)
CPC G05F 3/262 (2013.01) [G05F 3/242 (2013.01); H03M 1/66 (2013.01); H03M 1/742 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A controllable temperature coefficient bias circuit comprising a variable with temperature circuit having:
(a) a reference circuit having an output and a control port;
(b) a current control circuit including a first current control element having a first temperature coefficient coupled to the control port of the reference circuit and a second current control element having a second temperature coefficient, different from the first temperature coefficient, coupled to the control port of the reference circuit and coupled in parallel with the first current control element; and
(c) a current digital-to-analog circuit coupled to the output of the reference circuit and configured to output a current level that is selectively proportional to the output of the reference circuit.