US 11,719,979 B2
Array substrate, dimming liquid crystal panel, and display panel
Yue Du, Beijing (CN); Wei Guo, Beijing (CN); Ke Dai, Beijing (CN); Lei Guo, Beijing (CN); Liangliang Jiang, Beijing (CN); Jiaqing Liu, Beijing (CN); and Yuanhui Guo, Beijing (CN)
Assigned to HEFEI BOE DISPLAY TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 16/977,938
Filed by HEFEI BOE DISPLAY TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Nov. 28, 2019, PCT No. PCT/CN2019/121657
§ 371(c)(1), (2) Date Sep. 3, 2020,
PCT Pub. No. WO2021/102816, PCT Pub. Date Jun. 3, 2021.
Prior Publication US 2022/0326582 A1, Oct. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G02F 1/1337 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G02F 1/1343 (2006.01)
CPC G02F 1/133707 (2013.01) [G02F 1/1368 (2013.01); G02F 1/134336 (2013.01); G02F 1/136286 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An array substrate comprising:
a first transparent electrode layer with a plurality of slit structures, wherein the first transparent electrode layer comprises a plurality of domains, the plurality of domains comprise at least two types of domains, each of the plurality of domains is adjacent to different types of domains along both a row direction and a column direction, slit structures located in a same type of domain extend in a same direction, and slit structures located in different types of domains extend in different directions; and
a plurality of gate lines extending along the row direction and a plurality of data lines extending along the column direction, the plurality of gate lines and the plurality of data lines crossing to define a plurality of dimming regions arranged in an array, wherein each of the plurality of dimming regions is overlapped with the at least two types of domains in the first transparent electrode layer,
wherein:
each of the plurality of gate lines extends in a fold-line waveform along the row direction, and comprises a plurality of first fold line units arranged periodically, wherein each of the plurality of first fold line units comprises two first straight line segments symmetrically arranged with the column direction as a symmetry axis;
each of the plurality of data lines extends in a fold-line waveform along the column direction and comprises a plurality of second fold line units arranged periodically, wherein each of the plurality of second fold line units comprises a first subsegment and a second subsegment which are centrosymmetric, and the first subsegment and the second subsegment each comprise two second straight line segments symmetrically arranged with the row direction as a symmetric axis; and
the array substrate further comprises: a common electrode line located between adjacent two of the plurality of data lines, wherein the common electrode line extends in a fold-line waveform along the column direction and comprises a plurality of third fold line units arranged periodically, each of the plurality of third fold line units comprises a third subsegment and a fourth subsegment which are centrosymmetric, and the third subsegment and the fourth subsegment each comprise two third straight line segments symmetrically arranged with the row direction as a symmetric axis.