CPC G01R 31/31713 (2013.01) [G01R 31/318572 (2013.01); G11C 7/222 (2013.01); G11C 29/023 (2013.01)] | 20 Claims |
1. A memory device comprising:
a plurality of pins, comprising:
an isolation pin;
a test mode select pin configured to switch an operation mode of a memory die;
a test clock pin configured to receive a test clock; and
a test data pin configured to perform a data transmission;
a controller die coupled to the isolation pin, wherein the isolation pin is configured to provide an isolation control signal to indicate whether the memory die is to be isolated from the controller die; and
the memory die coupled to the test mode select pin, the test clock pin, and the test data pin.
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