CPC G01R 31/31705 (2013.01) [G01R 31/3177 (2013.01); H03K 5/26 (2013.01); H03K 19/1737 (2013.01); H03K 19/17764 (2013.01)] | 19 Claims |
1. An embedded logic analyzer of an integrated circuit, comprising:
a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions, the comparison block including a first comparison circuit, a second comparison circuit and a third comparison circuit, the first comparison circuit is configured to
shift one of the input data signal or a first shift data signal from the second comparison circuit to generate a second shift data signal, and
compare the second shift data signal with one of a reference data signal or a third shift data signal from the third comparison circuit to generate the comparison enable signal generated by the first comparison circuit;
an operation block configured to generate a data enable signal indicating a data capture timing; and
packer circuitry configured to generate a packer data signal.
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