CPC A61K 8/733 (2013.01) [A61K 8/0212 (2013.01); A61K 8/20 (2013.01); A61K 8/25 (2013.01); A61K 8/345 (2013.01); A61K 8/42 (2013.01); A61Q 19/00 (2013.01); A61Q 19/08 (2013.01); G01R 33/0354 (2013.01); G01R 33/1284 (2013.01); G06N 10/00 (2019.01); G11C 11/161 (2013.01); G11C 11/1653 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/18 (2013.01); G11C 11/44 (2013.01); G11C 7/1006 (2013.01); G11C 7/1075 (2013.01); G11C 2207/007 (2013.01); H01L 27/18 (2013.01); H01L 39/223 (2013.01)] | 20 Claims |
1. A cryogenic memory array chip configured to operate at below 10 K, comprising:
a plurality of magnetic Josephson junctions;
a readout circuit configured to read a magnetic state of the plurality of magnetic Josephson junctions; and
addressing logic configured to select a subset of the plurality of magnetic Josephson junctions, having a parallel data interface configured to transfer parallel data from the subset of the plurality of magnetic Josephson junctions at a rate of at least 20 GHz.
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