US 11,717,475 B1
System and method for cryogenic hybrid technology computing and memory
Oleg A. Mukhanov, Putnam Valley, NY (US); Alexander F. Kirichenko, Pleasantville, NY (US); Igor V. Vernik, Yorktown Heights, NY (US); Ivan P. Nevirkovets, Evanston, IL (US); and Alan M. Kadin, Princeton Junction, NJ (US)
Assigned to SeeQC, Inc., Elmsford, NY (US)
Filed by SeeQC, Inc., Elmsford, NY (US)
Filed on Aug. 8, 2022, as Appl. No. 17/818,349.
Application 17/818,349 is a continuation of application No. 15/888,601, filed on Feb. 5, 2018, granted, now 10,460,796, issued on Oct. 29, 2019.
Application 15/888,601 is a continuation of application No. 15/374,618, filed on Dec. 9, 2016, granted, now 9,887,000, issued on Feb. 6, 2018.
Application 15/374,618 is a continuation of application No. 14/643,078, filed on Mar. 10, 2015, granted, now 9,520,180.
Claims priority of provisional application 61/951,169, filed on Mar. 11, 2014.
Int. Cl. A61K 8/73 (2006.01); A61K 8/42 (2006.01); A61K 8/02 (2006.01); A61Q 19/00 (2006.01); A61K 8/34 (2006.01); A61K 8/20 (2006.01); A61Q 19/08 (2006.01); A61K 8/25 (2006.01); G06N 10/00 (2022.01); G01R 33/035 (2006.01); G01R 33/12 (2006.01); G11C 11/16 (2006.01); G11C 11/18 (2006.01); G11C 11/44 (2006.01); G11C 7/10 (2006.01); H01L 27/18 (2006.01); H01L 39/22 (2006.01)
CPC A61K 8/733 (2013.01) [A61K 8/0212 (2013.01); A61K 8/20 (2013.01); A61K 8/25 (2013.01); A61K 8/345 (2013.01); A61K 8/42 (2013.01); A61Q 19/00 (2013.01); A61Q 19/08 (2013.01); G01R 33/0354 (2013.01); G01R 33/1284 (2013.01); G06N 10/00 (2019.01); G11C 11/161 (2013.01); G11C 11/1653 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/18 (2013.01); G11C 11/44 (2013.01); G11C 7/1006 (2013.01); G11C 7/1075 (2013.01); G11C 2207/007 (2013.01); H01L 27/18 (2013.01); H01L 39/223 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A cryogenic memory array chip configured to operate at below 10 K, comprising:
a plurality of magnetic Josephson junctions;
a readout circuit configured to read a magnetic state of the plurality of magnetic Josephson junctions; and
addressing logic configured to select a subset of the plurality of magnetic Josephson junctions, having a parallel data interface configured to transfer parallel data from the subset of the plurality of magnetic Josephson junctions at a rate of at least 20 GHz.