CPC H04N 19/96 (2014.11) [H04N 19/124 (2014.11); H04N 19/159 (2014.11); H04N 19/176 (2014.11); H04N 19/18 (2014.11); H04N 19/66 (2014.11); H04N 19/91 (2014.11)] | 2 Claims |
1. An image decoder comprising:
circuitry; and
a memory coupled to the circuitry;
wherein the circuitry, in operation:
performs a first partitioning including using a first partition mode, without parsing first splitting information indicative of the first partition mode, to split a first block into a plurality of second blocks in response to that the first block is located adjacent to an edge of a picture and that the dimensions of the first block satisfy a first condition;
performs a second partitioning on the second block by parsing second splitting information indicative of a second partition mode, wherein the second partition mode allows at least one of a quad tree splitting and a binary splitting, and using the second partition mode to split the second block into a plurality of coding units (CUs), wherein the second partition mode prohibits the quad tree splitting of the second block in response to that the second block is located adjacent to the edge of the picture and that the dimensions of the second block satisfy a second condition, and
decodes the plurality of CUs.
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