US 11,716,480 B2
Selectable transcode engine systems and methods
Athanasios Leontaris, Cupertino, CA (US); Yaxiong Zhou, Fremont, CA (US); and Francesco Iacopino, Los Gatos, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Dec. 9, 2021, as Appl. No. 17/547,001.
Application 17/547,001 is a continuation of application No. 17/020,708, filed on Sep. 14, 2020, granted, now 11,206,415.
Prior Publication US 2022/0103844 A1, Mar. 31, 2022
Int. Cl. H04N 19/40 (2014.01); H04N 19/184 (2014.01); H04N 19/146 (2014.01); H04N 19/91 (2014.01)
CPC H04N 19/40 (2014.11) [H04N 19/146 (2014.11); H04N 19/184 (2014.11); H04N 19/91 (2014.11)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
video encoding pipeline circuitry comprising a first transcode engine and a second transcode engine configurable to encode source image data; and
processing circuitry configured to cause only the first transcode engine to encode a bin stream or both the first and second transcode engines to encode the bin stream based on determining:
whether a target throughput for the bin stream is greater than a throughput threshold; and
when the target throughput is greater than the throughput threshold, whether an expected latency associated with encoding the bin stream is greater than a latency threshold.