CPC H04N 19/40 (2014.11) [H04N 19/146 (2014.11); H04N 19/184 (2014.11); H04N 19/91 (2014.11)] | 20 Claims |
1. A system, comprising:
video encoding pipeline circuitry comprising a first transcode engine and a second transcode engine configurable to encode source image data; and
processing circuitry configured to cause only the first transcode engine to encode a bin stream or both the first and second transcode engines to encode the bin stream based on determining:
whether a target throughput for the bin stream is greater than a throughput threshold; and
when the target throughput is greater than the throughput threshold, whether an expected latency associated with encoding the bin stream is greater than a latency threshold.
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