US 11,716,090 B2
Interleaved analog-to-digital converter (ADC) gain calibration
Christopher A. Menkus, Aliso Viejo, CA (US); and Robert W. Kim, Aliso Viejo, CA (US)
Assigned to AyDee Kay LLC, Aliso Viejo, CA (US)
Filed by AyDeeKay LLC, Aliso Viejo, CA (US)
Filed on Jul. 22, 2022, as Appl. No. 17/870,831.
Application 17/870,831 is a continuation of application No. 17/322,876, filed on May 17, 2021, granted, now 11,424,752.
Claims priority of provisional application 63/110,895, filed on Nov. 6, 2020.
Prior Publication US 2023/0013568 A1, Jan. 19, 2023
Int. Cl. H03M 1/06 (2006.01)
CPC H03M 1/0609 (2013.01) [H03M 1/0612 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a set of analog-to-digital converters (ADCs) configured to provide quantized outputs corresponding to an input signal; and
a calibration engine, coupled to the set of ADCs, configured to provide full-scale reference corrections and DC offsets to the set of ADCs, wherein the calibration engine is configured to:
compute an average of the quantized outputs; and
determine, for a given ADC in the set of ADCs, a given full-scale reference correction in the full-scale reference corrections and a given DC offset in the DC offsets by comparing the average of the quantized outputs and a reference; and
wherein the calibration engine comprises:
full-scale reference generation circuits configured to generate full-scale reference voltages of full scales of each ADC in the set of ADCs, wherein the full-scale reference voltages correspond to variable components and a fixed component; and wherein the variable components correspond to the full-scale corrections of the full scales of the set of ADCs; and
a full-scale reference generator replica circuit configured to provide the fixed component, wherein the full-scale reference generator replica circuit is open-loop.