US 11,715,928 B2
Decoupling layer to reduce underfill stress in semiconductor devices
Priyanka Dobriyal, Santa Clara, CA (US); Susheel G. Jadhav, Los Gatos, CA (US); Ankur Agrawal, Chandler, AZ (US); Quan A. Tran, Fremont, CA (US); Raiyomand F. Aspandiar, Portland, OR (US); and Kenneth M. Brown, Tempe, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Aug. 29, 2019, as Appl. No. 16/554,789.
Prior Publication US 2021/0066882 A1, Mar. 4, 2021
Int. Cl. H01S 5/0234 (2021.01); G02F 1/015 (2006.01); H01S 5/0237 (2021.01); H01S 5/02234 (2021.01); H01S 5/02325 (2021.01); H01S 5/026 (2006.01)
CPC H01S 5/0234 (2021.01) [G02F 1/015 (2013.01); H01S 5/0237 (2021.01); H01S 5/02234 (2021.01); H01S 5/02325 (2021.01); H01S 5/0261 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) assembly comprising:
a support;
a semiconductor die including a device, the semiconductor die mounted to the support with the device facing the support;
a first layer comprising decoupling material on the device, the decoupling material in direct contact with the device; and
a second layer comprising an underfill material between the semiconductor die and the support, wherein the decoupling material is between the device and the underfill material and has a chemical composition that precludes covalent and ionic bonds with the underfill material.