US 11,715,787 B2
Self-aligned nanowire
Mark Armstrong, Portland, OR (US); Biswajeet Guha, Hillsboro, OR (US); Jun Sung Kang, Portland, OR (US); Bruce Beattie, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 29, 2021, as Appl. No. 17/514,058.
Application 17/514,058 is a continuation of application No. 16/632,856, granted, now 11,205,715, previously published as PCT/US2017/047758, filed on Aug. 21, 2017.
Prior Publication US 2022/0052178 A1, Feb. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/6681 (2013.01) [H01L 21/266 (2013.01); H01L 21/26506 (2013.01); H01L 21/30604 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/7853 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a nanowire or nanoribbon having an upper surface and a lower surface, the upper and lower surfaces of the nanowire or nanoribbon extending in a lateral direction;
an individual pair of spacers of one or more pairs of spacers, the individual pair of spacers comprising a first spacer adjacent to a first side of the nanowire or nanoribbon and a second spacer adjacent to a second side of the nanowire or nanoribbon; and
a layer of crystalline silicon below the nanowire or nanoribbon, the layer having one or more upper portions and a lower portion, the one or more upper portions of the layer each having a surface extending in the lateral direction, wherein the one or more upper portions of the layer comprises a first silicon crystal structure, and the lower portion of the layer comprises a second silicon crystal structure distinct from the first silicon crystal structure.