US 11,715,712 B2
Nonvolatile memory device and method for fabricating the same
Sung-Min Hwang, Hwaseong-si (KR); Ji Won Kim, Seoul (KR); Jae Ho Ahn, Seoul (KR); Joon-Sung Lim, Seongnam-si (KR); and Suk Kang Sung, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 18, 2021, as Appl. No. 17/323,076.
Claims priority of application No. 10-2020-0127835 (KR), filed on Oct. 5, 2020.
Prior Publication US 2022/0108963 A1, Apr. 7, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 23/562 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile memory device comprising:
an upper insulating layer;
a first substrate on the upper insulating layer;
an upper interlayer insulating layer on the first substrate;
a plurality of word lines stacked on the first substrate in a first direction and extending through a partial portion of the upper interlayer insulating layer;
a lower interlayer insulating layer on the upper interlayer insulating layer;
a second substrate on the lower interlayer insulating layer;
a lower insulating layer on the second substrate; and
a dummy pattern composed of dummy material, the dummy pattern is disposed in a trench formed in at least one of the first and second substrates, wherein the trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate, the trench extending solely within the at least one of the first and second substrates.