US 11,715,693 B2
Dielectric waveguide channel for interconnecting dies in a semiconductor package usable in a computing device and method of manufacture
Georgios Dogiamis, Chandler, AZ (US); Aleksandar Aleksov, Chandler, AZ (US); Adel A. Elsherbini, Chandler, AZ (US); Henning Braunisch, Phoenix, AZ (US); Johanna M. Swan, Scottsdale, AZ (US); and Telesphor Kamgaing, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 29, 2019, as Appl. No. 16/397,923.
Claims priority of application No. 20190100126 (GR), filed on Mar. 15, 2019.
Prior Publication US 2020/0294940 A1, Sep. 17, 2020
Int. Cl. H01L 23/538 (2006.01); H01L 23/66 (2006.01); G02B 6/30 (2006.01); H01P 3/16 (2006.01); H01P 11/00 (2006.01)
CPC H01L 23/538 (2013.01) [G02B 6/30 (2013.01); H01L 23/66 (2013.01); H01P 3/16 (2013.01); H01P 11/006 (2013.01); H01L 2223/6627 (2013.01)] 16 Claims
OG exemplary drawing
 
11. A method of forming a waveguide that is to be coupled with a package substrate of a semiconductor package, wherein the method comprises:
laminating a waveguide dielectric material on a sacrificial layer of a carrier;
developing the waveguide dielectric material into one or more waveguide channels; and
positioning an adhesive material on the waveguide dielectric material.