US 11,715,514 B2
Latch bit cells
Russell J. Schreiber, Austin, TX (US); and John J. Wuu, Ft. Collins, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/359,209.
Claims priority of provisional application 63/185,207, filed on May 6, 2021.
Prior Publication US 2022/0359015 A1, Nov. 10, 2022
Int. Cl. G11C 11/40 (2006.01); G11C 11/4096 (2006.01); G11C 11/408 (2006.01); G11C 7/10 (2006.01); G11C 11/4074 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 7/106 (2013.01); G11C 7/1009 (2013.01); G11C 7/1087 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A latch bit cell of a static random access memory (SRAM) comprising:
a write portion of the latch bit cell, the write portion of the latch bit cell including,
an input node to receive data to be written to the write portion of the latch bit cell, wherein the data can be either a logical one or a logical zero;
a pass gate coupled to the input node and responsive to supply the data on the input node to a first node of the latch bit cell responsive to write word line signals being asserted;
an inverter coupled to the first node to supply inverted data;
a keeper circuit coupled to the inverter and configured to maintain the data on the first node when the write word line signals are deasserted and wherein an output of the keeper circuit is disabled responsive to the write word line signals being asserted during a write operation; and
a read portion of the latch bit cell coupled to receive read word line signals and responsive to assertion of the read word line signals to supply output data on an output node of the read portion of the latch bit cell, the output data corresponding to the data on the first node; and
wherein the read portion of the latch bit cell is formed by a first plurality of transistors having a first threshold voltage and the write portion of the latch bit cell, including the pass gate, the inverter, and the keeper circuit, is formed by a second plurality of transistors having a second threshold voltage, the second threshold voltage being higher than the first threshold voltage.